In a typical static CMOS register design there are two stages: a master latch stage and a slave latch stage. Additionally, the prior art static CMOS registers require the use of both PMOS and NMOS FETs in each pass gate within each stage. That inclusion of both PMOS and NMOS devices in each pass gate requires that two clock signals, clock and inverse clock, be provided to both pass gates in such static registers.
The use of two serially connected stages, the master stage and slave stage, plus the inclusion of a PMOS device in each stage contributes a double factor to the setup time of the register. Each of the master stage and the slave stage contributes a set-up time since the data has to pass through the master stage with a first set-up time before the output data is provided to the slave stage with a second set-up time. Additionally, the need to provide both the clock and inverse clock signals to both the master and slave stages, as well as the inclusion of both PMOS and NMOS devices in both stages of the static register, requires the allocation of wafer surface area to provide those signal traces and components to implement that design.
It would be desirable to have a register that includes a single stage, only requires the use of a single clock signal and only uses PMOS devices during a precharge phase that occurs within an initial clock pulse so that the actual switching setup time during an evaluation phase is determined only by the switching time of NMOS devices. It would further be advantageous to have a self-timed clock circuit to reset the clock level to zero during the evaluation phase. It would be a further advantage to have a self-timed clock circuit that could be used to interface with multiple registers on the same die. The dynamic register of the present invention provides all of these advantages over the static registers of the prior art.